Lossless compressions use data segments of configurable sizes, which are compressed. This compressed data is then stored in caches until it is written back to memory. However, by compressing data, unused holes in the physical address space are created. Depending on how the compressed data is stored in physical address space, there can be uneven use of system level resources such as the caches. Caches store data at a cache line granularity, and use the most frequently used bits to route data into banks. The mismatch between the compressed block sizes and the cache line size can result in irregular use of the cache resources (e.g., banks). This irregular use is created by the compressed data clearing unused bits in the physical address, which are used in cache indexing. For example, such a case occurs when compressing a 256 byte block into 128 bytes, which will clear the address bits for the compressed data in the physical address. Lower address bits are typically used for cache selection decisions in order to create balanced accesses (since they change frequently). If bit W of the lower address bits would normally be used to select a cache bank, the compressed data will always be located in half the banks/cache because the value will always be the same when bit W is cleared (i.e., after compression bit W=0). Similarly, if two bits, such as bit W and bit Y, would normally be used to select a cache bank, the compressed data will always be located in half the banks/cache because, while the value of bit Y may change (i.e., after compression bit Y will equal 0 or 1), the value of bit W would remain static (i.e., bit W=0), and therefore the bank selection bits W and Y together may combine for only two of four bank selection options (i.e., bits Y and W=00 or 10, instead of 00, 01, 10, or 11).